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NCP1631
Provided the low bandwidth of the regulation loop, sharp
variations of the load, may result in excessive over and
under ? shoots. Over ? shoots are limited by the Over ?
Voltage Protection (see OVP section). To contain the
under ? shoots, an internal comparator monitors the
feed ? back signal (V pin2 ) and when V pin2 is lower than
95.5% of its nominal value, it connects a 230 m A current
source to speed ? up the charge of the compensation
capacitor (C pin5 ). Finally, it is like if the comparator
multiplied the error amplifier gain by 10.
One must note that this circuitry for under ? shoots
limitation, is not enabled during the start ? up sequence of
the PFC stage but only once the converter has stabilized
(that is when the “ pfcOK ” signal of the block diagram, is
high). This is because, at the beginning of operation, the
pin5 capacitor must charge slowly and gradually for a soft
start ? up.
Rzcd2
Zero Current Detection
While the on time is constant, the core reset time varies
with the instantaneous input voltage. The NCP1631
determines the demagnetization completion by sensing the
inductor voltage, more specifically, by detecting when the
inductor voltage drops to zero.
Practically, an auxiliary winding in flyback
configuration is taken off of the boost inductor and gives a
scaled down version of the inductor voltage that is usable
by the controller (Figure 12). In that way, the ZCD voltage
(“V AUX ”) falls and starts to ring around zero volts when the
inductor current drops to zero. The NCP1631 detects this
falling edge and allows the next driver on time.
Figure 1 shows how it is implemented.
For each phase, a comparator detects when the voltage
of the ZCD winding exceeds 0.5 V. When this is the case,
the coil is in demagnetization phase and the latch L ZCD is
set. This latch is reset when the next driver pulse occurs.
Vzcd1
SET1
CLK1
(from phase
management
(from PH1 PWM
comparator)
1 ZCD2
Negative
and
positive
clamp
16 ZCD1
Negative
and
positive
clamp
Rzcd1
V DMG1
+
?
L ZCD
0.5 V
200 ? m s
delay
OFF
(from Fault
S
Q
Q ZCD
R
AND1
Qzcd1
block)
Q
R
S DT
PWM
latch
PH1 Vcc
S
Q
R
In ? rush output
buffe r 1
reset signal
Vin
L1
DRV1
14 M1
Vin L2
D1
D2
Vout
latch PH2
S
management
block)
+
?
0.5 V
V DMG2
S
R
Q
Vzcd2
Qzcd2
CLK2
(from phase
management
block)
PWM output
SET2 buffe r 2
Vcc
Q
R
In ? rush reset signal
(from PH2 PWM comparator)
DRV2
11 M2
Cbulk
Cbulk
Figure 11. Zero Current Detection
To prevent negative voltages on the ZCD pins (ZCD1 for
phase 1 and ZCD2 for phase 2), these pins are internally
clamped to about 0 V when the voltage applied by the
corresponding ZCD winding is negative. Similarly, the
ZCD pins are clamped to V ZCD(high) (10 V typical), when
the ZCD voltage rises too high. Because of these clamps,
a resistor (R ZCD of Figure 11) is necessary to limit the
current from the ZCD winding to the ZCD pin. The clamps
are designed to respectively source and sink 5 mA
minimum. It is recommended not to exceed this 5 mA level
within the ZCD clamps for a proper operation.
At startup or after an inactive period (because of a
protection that has tripped for instance), there is no energy
in the ZCD winding and therefore no voltage signal to
activate the ZCD comparator. This means that the driver
will never turn on. To avoid this, an internal watchdog
timer is integrated into the controller. If the driver remains
low for more than 200 m s (typical), the timer sets the L ZCD
latch as the ZCD winding signal would do. Obviously, this
200 ? m s delay acts as a minimum off ? time if there is no
demagnetization winding while it has no action if there is
a ZCD voltage provided by the auxiliary winding.
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